1. Technical Field
The present invention generally relates to processing data streams. More specifically, the present invention relates to processing data streams that repetitively access hardware registers of a processor to process a data stream.
2. Description of the Related Art
Typically, streaming processors are coprocessors that interact with a host processor and are generally implemented as an application specific integrated circuit (ASIC). For example, the ASIC can include forty-eight arithmetic logic units (ALUs) that access a register file of the ASIC, and a streaming memory unit transfers streaming data between the register file of the ASIC and an off-chip memory. Using ASIC coprocessors, flexibility is sacrificed. For example, a computing model that is data-centric can work well for a traditional graphical processing unit (GPU) or digital signal processing (DSP) type applications; however, this computing model that is data-centric typically performs poorly for general purpose processing where data access can be more randomized or where memory access patterns are less predictable. Moreover, while an ASIC streaming coprocessor can use arrays, array dimension, array word length, stride, etc. are fixed when processing a specific data stream. Furthermore, there can be additional latency in an application executing on the host processor accessing data processed by the ASIC streaming coprocessor.